The present application relates to integrated circuits, and more particularly, to mixed ionic electronic conductor-based memory cell access devices formed using a subtractive etch process.
Mixed ionic electronic conductors (MIEC) are being explored as access devices for non-volatile memories such as, for example, phase-change memory, resistive random access memory, and spin-torque transfer random access memory. MIEC-based access devices having high voltage margins for use in large memory arrays are desirable. Study shows that MIEC voltage margins increase as the confined volume of MIEC material decreases.
The MIEC-based memory cell access devices are typically formed using an additive damascene process in which a dielectric material layer is patterned to include vias therein. The MIEC material is subsequently deposited within the vias and thereafter any MIEC material that is located outside the vias is removed utilizing a planarization process, e.g., chemical mechanical planarization (CMP).
FIG. 1 shows a MIEC-based memory cell access device 100 formed by the additive damascene process. The MIEC-based memory cell access device 100 includes a MIEC material portion 120 sandwiched between a bottom electrode 110 and a top electrode 130. The MIEC material portion 120 is formed by filling a via formed in a dielectric material layer 140. Several issues are associated with this conventional damascene process in forming the MIEC-based memory cell access device 100. First, the via etching process typically forms a via having a tapered profile; the MIEC material portion 120 formed within the via is also tapered to have a smaller cross-section area at the bottom of the MIEC material portion 120 than at the top of the MIEC material portion 120. Thus, the contact area between the MIEC material portion 120 and the bottom electrode 110 is smaller than that between the MIEC material portion 120 and the top electrode 130. The different contact areas lead to asymmetric current vs. voltage (I-V) characteristics during bi-directional electrical operation of the access device. This device asymmetry also results in an increase in the low leakage current of the access device. Moreover, it is known that the CMP process that is employed to remove the excess MIEC material from the top of the dielectric material layer 140 forms surface defects on the MIEC material portion 120, which adversely affect the device performance. Therefore a need exists to overcome the problems with the prior art as discussed above.